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1/16 l6562 june 2004 1 features realised in bcd technology transition-mode control of pfc pre- regulators proprietary multiplier design for minimum thd of ac input current very precise adjustable output overvoltage protection ultra-low ( 70 a) start-up current low ( 4 ma) quiescent current extended ic supply voltage range on-chip filter on current sense disable function 1% (@ tj = 25 c) internal reference voltage -600/+800ma totem pole gate driver with uvlo pull-down and voltage clamp dip-8/so-8 packages 1.1 applications pfc pre-regulators for: ? iec61000-3-2 compliant smps (tv, desktop pc, monitor) up to 300w ? hi-end ac-dc adapter/charger ? entry level server & web server 2 description the l6562 is a current-mode pfc controller oper- ating in transition mode (tm). pin-to-pin compati- ble with the predecessor l6561, it offers improved performance. transition-mode pfc controller figure 2. block diagram + - multiplier and thd optimizer v ref2 overvoltage detection voltage regulator uvlo internal supply 7v + - 2.5v r1 r2 r s q + - driver starter + - zero current detector disable 2.1 v 1.6 v v cc 8 1 23 4 zcd v cc inv comp mult cs gd 7 5 gnd 6 25 v 40k 5pf 15 v starter stop rev. 6 fi gure 1. p ac k ages table 1. order codes part number package L6562N dip-8 l6562d so-8 l6562dtr tape & reel dip-8 so-8
l6562 2/16 2 description (continued) the highly linear multiplier includes a special circuit, able to reduce ac input current distortion, that allows wide-range-mains operation with an extremely low thd, even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @tj = 25c) internal voltage reference. the device features extremely low consumption ( 70 a before start-up and <4 ma running) and includes a disable function suitable for ic remote on/off, which makes it easier to comply with energy saving norms (blue angel, energystar, energy2000, etc.). an effective two-step ovp enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. the totem-pole output stage, capable of 600 ma source and 800 ma sink current, is suitable for big mos- fet or igbt drive which, combined with the other features, makes the device an excellent low-cost solu- tion for en61000-3-2 compliant smps's up to 300w. table 2. absolute maximum ratings figure 3. pin connection (top view) table 3. thermal data symbol pin parameter value unit v cc 8 ic supply voltage (icc = 20 ma) self-limited v igd 7 output totem pole peak current 0.8 a --- 1 to 4 analog inputs & outputs -0.3 to 8 v izcd 5 zero current detector max. current -50 (source) 10 (sink) ma p tot power dissipation @tamb = 50c (dip-8) (so-8) 1 0.65 w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c symbol parameter so8 minidip unit r th j-amb max. thermal resistance, junction-to-ambient 150 100 c/w zcd inv comp mult cs vcc gd gnd 1 2 3 4 8 7 6 5
3/16 l6562 table 4. pin description n pin function 1 inv inverting input of the error amplifier. the information on the output voltage of the pfc pre- regulator is fed into the pin through a resistor divider. 2 comp output of the error amplifier. a compensation network is placed between this pin and inv (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low thd. 3 mult main input to the multiplier. this pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 cs input to the pwm comparator. the current flowing in the mosfet is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine mosfet?s turn-off. 5 zcd boost inductor?s demagnetization sensing input for transition-mode operation. a negative-going edge triggers mosfet?s turn-on. 6 gnd ground. current return for both the signal part of the ic and the gate driver. 7 gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak current of 600 ma source and 800 ma sink. the high-level voltage of this pin is clamped at about 12v to avoid excessive gate voltages in case the pin is supplied with a high vcc. 8 vcc supply voltage of both the signal part of the ic and the gate driver. the supply voltage upper limit is extended to 22v min. to provide more headroom for supply voltage changes. table 5. electrical characteristics (t j = -25 to 125c, v cc = 12, c o = 1 nf; unless otherwise specified) symbol parameter test condition min. typ. max. unit supply voltage v cc operating range after turn-on 10.3 22 v v ccon turn-on threshold (1) 11 12 13 v v ccoff turn-off threshold (1) 8.7 9.5 10.3 v hys hysteresis 2.2 2.8 v v z zener voltage i cc = 20 ma 22 25 28 v supply current i start-up start-up current before turn-on, v cc =11v 40 70 a i q quiescent current after turn-on 2.5 3.75 ma i cc operating supply current @ 70 khz 3.5 5 ma i q quiescent current during ovp (either static or dynamic) or v zcd =150 mv 2.2 ma multiplier input i mult input bias current v vff = 0 to 4 v -1 a v mult linear operation range 0 to 3 v output max. slope v mult = 0 to 0.5v v comp = upper clamp 1.65 1.9 v/v k gain (2) v mult = 1 v, v comp = 4 v 0.5 0.6 0.7 1/v error amplifier v inv voltage feedback input threshold t j = 25 c 2.465 2.5 2.535 v 10.3 v < vcc < 22 v (1) 2.44 2.56 line regulation vcc = 10.3 v to 22v 2 5 mv i inv input bias current v inv = 0 to 3 v -1 a v cs ? v mult ? ---------------------
l6562 4/16 (1) all parameters are in tracking (2) the multiplier output is given by: (3) parameters guaranteed by design, functionality tested in production. g v voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4v, v inv = 2.4 v -2 -3.5 -5 ma sink current v comp = 4v, v inv = 2.6 v 2.5 4.5 ma v comp upper clamp voltage i source = 0.5 ma 5.3 5.7 6 v lower clamp voltage i sink = 0.5 ma (1) 2.1 2.25 2.4 v current sense comparator i cs input bias current v cs = 0 -1 a t d(h-l) delay to outpu t 200 350 ns v cs clamp current sense reference clamp v comp = upper clamp 1.6 1.7 1.8 v v csoffset current sense offset v mult = 0 30 mv v mult = 2.5v 5 zero current detector v zcdh upper clamp voltage i zcd = 2.5 ma 5.0 5.7 6.5 v v zcdl lower clamp voltage i zcd = -2.5 ma 0.3 0.65 1 v v zcda arming voltage (positive-going edge) (3) 2.1 v v zcdt triggering voltage (negative-going edge) (3) 1.6 v i zcdb input bias current v zcd = 1 to 4.5 v 2a i zcdsrc source current capability -2.5 -5.5 ma i zcdsnk sink current capability 2.5 ma v zcddis disable threshold 150 200 250 mv v zcden restart threshold 350 mv i zcdres restart current after disable 30 75 a starter t start start timer period 75 130 300 s output overvoltage i ovp dynamic ovp triggering current 35 40 45 a hys hysteresis (3) 30 a static ovp threshold (1) 2.1 2.25 2.4 v gate driver v oh dropout voltage i gdsource = 20 ma 22.6 i gdsource = 200 ma 2.5 3 v v ol i gdsink = 200 ma 0.9 1.9 v t f voltage fall time 30 70 ns t r voltage rise time 40 80 ns v oclamp output clamp voltage i gdsource = 5ma; vcc = 20v 10 12 15 v uvlo saturation v cc = 0 to v ccon , i sink =10ma 1.1 v table 5. electrical characteristics (continued) (t j = -25 to 125c, v cc = 12, c o = 1 nf; unless otherwise specified) symbol parameter test condition min. typ. max. unit v cs kv mult v comp 2.5 ? () ?? =
5/16 l6562 3 typical electrical characteristics figure 4. supply current vs. supply voltage figure 5. start-up & uvlo vs. t j figure 6. ic consumption vs. t j figure 7. vcc zener voltage vs. t j v cc(v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 i cc (ma) 0 5 10 15 20 co = 1nf f = 70 khz t j = 25c 25 tj ( c) v cc-on (v) v cc-off (v) -50 0 50 100 150 9 9.5 10 10.5 11 11.5 12 12.5 -50 0 50 100 150 0.02 0.05 0.1 0.2 0.5 1 2 5 10 icc [ma] operating quiescent disabled or during ovp before start-up vcc = 12 v co = 1 nf f = 70 khz tj (c) tj (c) vcc z (v) -50 0 50 100 150 22 23 24 25 26 27 28
l6562 6/16 figure 8. feedback reference vs. t j figure 9. ovp current vs. t j figure 10. e/a output clamp levels vs. t j figure 11. delay-to-output vs. t j figure 12. multiplier characteristic figure 13. multiplier gain vs. t j v ref (v) -50 0 50 100 150 2.4 2.45 2.5 2.55 2.6 vcc = 12 v tj (c) i ovp (a) -50 0 50 100 150 39 39.5 40 40.5 41 vcc = 12 v tj (c) tj (c) vpin2 (v) -50 0 50 100 150 2 3 4 5 6 upper clamp lower clamp vcc = 12 v tj (c) t d(h-l) (ns) -50 0 50 100 150 0 100 200 300 400 500 vcc = 12 v v mult (pin 3) (v) v comp (pin 2) (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 v cs (pin 4) 2.6 3.0 3.2 4 . 5 5.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 (v) 4.0 2.8 upper voltage clamp 3.5 tj (c) k -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1 vcc = 12 v v comp =4 v v mult =1v
7/16 l6562 figure 14. vcs clamp vs. t j figure 15. start-up timer vs. t j figure 16. zcd clamp levels vs. t j figure 17. zcd source capability vs. t j figure 18. gate-drive output low saturation figure 19. gate-drive output high saturation tj (c) v csx (v) -50 0 50 100 150 1 1.2 1.4 1.6 1.8 2 vcc = 12 v v comp = upper clamp tj (c) tstart (s) -50 0 50 100 150 100 110 120 130 140 150 vcc = 12 v tj (c) v zcd (v) -50 0 50 100 150 0 1 2 3 4 5 6 7 vcc = 12 v i zcd = 2.5 ma upper clamp lower clamp tj (c) i zcdsrc (ma) -50 0 50 100 150 -8 -6 -4 -2 0 vcc = 12 v v zcd = lower clamp v pin7 [v] 0 200 400 600 800 1,000 0 1 2 3 4 i gd [ma] tj = 25 c vcc = 11 v sink 0 100 200 300 400 500 600 700 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 v pin7 [v] i gd [ma] tj = 25 c vcc = 11 v source vcc - 2.0 vcc - 2.5 vcc - 3.0 vcc - 3.5 vcc - 4.0
l6562 8/16 figure 20. gate-drive clamp vs. t j figure 21. uvlo saturation vs. t j tj (c) vpin7 clamp (v) -50050100150 10 11 12 13 14 15 vcc = 20 v tj (c) -50 0 50 100 150 0.5 0.6 0.7 0.8 0.9 1 1.1 vcc = 0 v vpin7 (v) 4 application information 4.1 overvoltage protection under steady-state conditions, the voltage control loop keeps the output voltage vo of a pfc pre-regulator close to its nominal value, set by the resistors r1 and r2 of the output divider. neglecting ripple compo- nents, the current through r1, i r1 , equals that through r2, i r2 . considering that the non-inverting input of the error amplifier is internally referenced at 2.5v, also the voltage at pin inv will be 2.5v, then: . if the output voltage experiences an abrupt change ? vo > 0 due to a load drop, the voltage at pin inv will be kept at 2.5v by the local feedback of the error amplifier, a network connected between pins inv and comp that introduces a long time constant to achieve high pf (this is why ? vo can be large). as a result, the current through r2 will remain equal to 2.5/r2 but that through r1 will become: . the difference current ? i r1 =i' r1 -i r2 =i' r1 -i r1 = ? vo/r1 will flow through the compensation network and en- ter the error amplifier output (pin comp). this current is monitored inside the l6562 and if it reaches about 37 a the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv- ered to the output. as the current exceeds 40 a, the ovp is triggered (dynamic ovp): the gate-drive is forced low to switch off the external power transistor and the ic put in an idle state. this condition is main- tained until the current falls below approximately 10 a, which re-enables the internal starter and allows switching to restart. the output ? vo that is able to trigger the dynamic ovp function is then: . an important advantage of this technique is that the ov level can be set independently of the regulated output voltage: the latter depends on the ratio of r1 to r2, the former on the individual value of r1. another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ? vo. since ? vo << vo, the tolerance on the absolute value will be proportionally reduced. example: vo = 400 v, ? vo = 40 v. then: r1=40v/40 a=1m ? ; r2=1m ? 2.5/(400-2.5)=6.289k ? . the tol- erance on the ovp level due to the l6562 will be 400.12=4.8v, that is 1.2% of the regulated value. i r2 2.5 r2 ------- - i r1 vo 2.5 ? r1 --------------------- - === i ' r1 vo 2.5 ? vo ? + r1 --------------------------------------- - = vo ? r1 40 10 6 ? ?? =
9/16 l6562 when the load of a pfc pre-regulator is very low, the output voltage tends to stay steadily above the nom- inal value, which cannot be handled by the dynamic ovp. if this occurs, however, the error amplifier out- put will saturate low; hence, when this is detected, the external power transistor is switched off and the ic put in an idle state (static ovp). normal operation is resumed as the error amplifier goes back into its lin- ear region. as a result, the l6562 will work in burst-mode, with a repetition rate that can be very low. when either ovp is activated the quiescent consumption of the ic is reduced to minimize the discharge of the vcc capacitor and increase the hold-up capability of the ic supply system. 4.2 thd optimizer circuit the l6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the ac input current near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmonic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instan- taneous line voltage is very low. this effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. figure 22. thd optimization: standard tm pfc controller (left side) and l6562 (right side) to overcome this issue the circuit embedded in the l6562 forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. this will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high- frequency filter capacitor after the bridge. the effect of the circuit is shown in figure 23, where the key waveforms of a standard tm pfc controller are compared to those of the l6562. essentially, the circuit artificially increases the on-time of the power switch with a positive offset added to imains vdrain imains vdrain input current input current mosfet's drain voltage mosfet's drain voltage rectified mains voltage rectified mains voltage input current input current
l6562 10/16 the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. to maximally benefit from the thd optimizer circuit, the high-frequency filter capacitor after the bridge rec- tifier should be minimized, compatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dead-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre- regulator - thus making the action of the optimizer circuit little effective. figure 23. typical application circuit (250w, wide-range mains) figure 24. demo board (eval6562-80w, wide-range mains): electrical schematic ntc 2.5 ? 8 3 bridge stbr606 r1 1.5 m ? c1 1 f 400v r3 22 k ? c29 22 f 25v fuse 5a/250v r4 180 k ? d8 1n4150 d2 1n5248b r14 100 ? c5 12 nf r6 68 k ? t 5 6 l6562 7 21 r7 10 ? mos stp12nm50 7 c/w heat sink 4 r11 750 k ? c6 100 f 450v vo=400v po=250w - vac (85v to 265v) r9 0.33 ? 1w r13 9.53 k ? + - c4 100 nf c2 10nf d1 stth5l06 r50 10 k ? c3 2.2 f r2 1.5 m ? r5 180 k ? r10 0.33 ? 1w r12 750 k ? c23 680 nf boost inductor spec: eb0057-c ( coilcraft ) d3 1n5406 ntc 2.5 ? 8 3 bridge df06m r1 750 k ? c1 0.47 f 400v r3 10 k ? c29 22 f 25v fuse 4a/250v r4 180 k ? d8 1n4150 d2 1n5248b r14 100 ? c5 12 nf r6 68 k ? t 5 6 l6562 7 21 r7 33 ? mos stp8nm50 4 r11 750 k ? c6 47 f 450v vo=400v po=80w - vac (85v to 265v) r9 0.82 ? 0.6 w r13 9.53 k ? + - c4 100 nf c2 10nf d1 stth1l06 r50 12 k ? c3 680 nf r2 750 k ? r5 180 k ? r10 0.82 ? 0.6 w r12 750 k ? c23 330 nf boost inductor spec (itacoil e2543/e) e25x13x7 core, 3c85 ferrite 1.5 mm gap for 0.7 mh primary inductance primary: 105 turns 20x0.1 mm secondary: 11 turns 0.1 mm
11/16 l6562 figure 25. eval6562-80w: pcb and component layout (top view, real size: 57 x 108 mm) table 6. evaL6562N: evaluation results at full load table 7. evaL6562N: evaluation results at half load vin (v ac ) pin (w) vo (v dc ) ? vo(v pk-pk ) po (w) (%) pf thd (%) 85 86.4 394.79 12.8 80.16 92.8 0.998 3.6 110 84.6 394.86 12.8 80.20 94.8 0.996 4.2 135 83.8 394.86 12.8 80.20 95.7 0.991 4.9 175 83.2 394.87 15.5 80.20 96.4 0.981 6.5 220 82.9 394.87 15.7 80.20 96.7 0.956 7.8 265 82.7 394.87 15.9 80.20 97.0 0.915 9.2 note: measurements done with the line filter shown in figure 23 vin (v ac ) pin (w) vo (v dc ) ? vo(v pk-pk ) po (w) (%) pf thd (%) 85 42.8 394.86 6.6 40.20 93.9 0.994 5.5 110 42.5 394.90 6.6 40.20 94.6 0.985 6.2 135 42.5 394.91 6.7 40.20 94.6 0.967 7.1 175 42.5 394.93 8.0 40.19 94.6 0.939 8.3 220 42.6 394.94 8.2 40.19 94.3 0.869 9.8 265 42.6 394.94 8.3 40.19 94.3 0.776 11.4 note: measurements done with the line filter shown in figure 23
l6562 12/16 table 8. evaL6562N: no-load measurements figure 26. line filter (not tested for emi compliance) used for evaL6562N evaluation vin (v ac ) pin (w) vo (v dc ) ? vo(v pk-pk ) po (w) 85 0.4 396.77 0.45 0 110 0.3 396.82 0.55 0 135 0.3 396.83 0.60 0 175 (*) 0.4 396.90 1.00 0 220 (*) 0.4 396.95 1.40 0 265 (*) 0.5 396.98 1.65 0 (*) vcc = 12v supplied externally to the ac source b82732 47 mh, 1.3a epcos b81133 470 nf, x2 epcos to evaL6562N b81133 680 nf, x2 epcos
13/16 l6562 figure 27. dip-8 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060 dip-8
l6562 14/16 figure 28. so-8 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 note: (1) dimensions d does not include mold flash, protru- sions or gate burrs. mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). so-8 0016023 c
15/16 l6562 table 9. revision history date revision description of changes january 2004 5 first issue june 2004 6 modified the style-look in compliance with the ?corporate technical publications design guide?. changed input of the power amplifier connected to multiplier (fig. 2).
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 16/16 l6562

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